1. Field of the Invention
This invention relates to integrated circuit packaging technology, and more particularly, to a flip-chip packaging technology for use to fabricate a dual-chip integrated circuit package that includes two semiconductor chips in a single package unit.
2. Description of Related Art
The flip-chip packaging technology is an advanced integrated circuit packaging technology that allows the overall package size to be made very compact. The flip-chip package configuration differs from conventional art particularly in that it includes at least one semiconductor chip mounted in an upside-down manner over substrate or another semiconductor chip and electrically coupled to the same by means of solder bumps which are reflowed to solder pads on the flip-chip mounting surface. After the flip chip is readily bonded in position, however, a gap would be undesirably left between the chip and its underlying surface, which, if not underfilled, would easily cause the flip chip to suffer from fatigue cracking and electrical failure due to thermal stress when the entire package structure is being subjected to high-temperature conditions. As a solution to this problem, it is an essential step in flip-chip package fabrication to fill an underfill material, such as epoxy resin, into such a gap. The underfilled resin, when hardened, can serve as a mechanical reinforcement for the flip chip to cope against thermal stress. The involved fabrication process is customarily referred to as flip-chip underfill. By conventional flip-chip underfill technology, however, the underfill material would easily flow to other areas, causing undesired flash that would adversely affect subsequent wire-bonding process or passive-component mounting.
One solution to the foregoing problem is disclosed in the U.S. Pat. No. 5,218,234, which teaches the forming of a recessed portion in substrate to help prevent resin flash. In addition, the U.S. Pat. No. 5,120,678 teaches the forming of a darn structure on substrate to confine the underfill material within predefined area. These two patented technologies, however, are unsuitable for use on a dual-chip package structure wherein one chip is mounted in flip-chip manner over another one. This is because that it is required to form bonding pads on the active surface of the underlying chip (i.e., the carrier chip) for solder bonding to the overlying chip (i.e., the flip chip), and these bonding pads are located very near to the edge of the flip chip. In this case, the use of the patented technology of U.S. Pat. No. 5,120,678 would nevertheless cause resin flash on the bonding pads. As to the U.S. Pat. No. 5,218,234, since the underlying chip is provided without solder mask and with a plurality of exposed bonding pads, it is also unsuitable for use on a dual-chip package structure to solve the flash problem.
It is therefore an objective of this invention to provide a new flip-chip packaging technology that can help prevent the underfill material used in the flip-chip underfill process from flashing to other unintended areas and causing contamination to solder pads.
In accordance with the foregoing and other objectives, the invention proposes a new flip-chip packaging technology.
The flip-chip packaging technology comprises the following procedural steps: preparing a first semiconductor chip having an active surface and an inactive surface, with the active surface being formed with a chip-bonding area; wherein a plurality of inner bonding pads are formed in the chip-bonding area, while a plurality of outer bonding pads are formed beyond the chip-bonding area on the active surface; forming a coating layer over the active surface of the first semiconductor chip; etching away selected portions of the coating layer to expose the inner bonding pads and the outer bonding pads and meanwhile forming a flash-barrier structure around the chip-bonding area to separate the chip-bonding area from the outer bonding pads; electrically coupling a second semiconductor chip by means of solder bumps to the chip-bonding area on the first semiconductor chip, with a gap existing between the first semiconductor chip and the second semiconductor chip; and forming an underfill layer in the gap between the first semiconductor chip and the second semiconductor chip.
The flash-barrier structure can be either a protruded dam structure over the first semiconductor chip, or a groove in the coating layer, which can help prevent the underfill material from flowing to the areas therebeyond.
In terms of structure, the flip-chip packaging technology of the invention comprises: a first semiconductor chip having an active surface and an inactive surface, with the active surface being formed with a chip-bonding area; wherein a plurality of inner bonding pads are formed in the chip-bonding area, while a plurality of outer bonding pads are formed beyond the chip-bonding area on the active surface; a flash-barrier structure formed around the chip-bonding area of the first semiconductor chip to separate the chip-bonding area from the outer bonding pads; a second semiconductor chip electrically coupled to the first semiconductor chip by means of solder bumps to the chip-bonding area on the first semiconductor chip, with a gap existing between the first semiconductor chip and the second semiconductor chip; and an underfill layer formed in the gap between the first semiconductor chip and the second semiconductor chip.
The coating layer can be formed from, for example, polyimide or epoxy resin, and most preferably from polyimide.